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ISL6237
Data Sheet March 16, 2007 FN6418.1
High-Efficiency, Quad-Output, Main Power Supply Controllers for Notebook Computers
The ISL6237 dual step-down, switch-mode power-supply (SMPS) controller generates logic-supply voltages in battery-powered systems. The ISL6237 includes two pulse-width modulation (PWM) controllers, 5V/3.3V and 1.5V/1.05V. The output of SMPS1 can also be adjusted from 0.7V to 5.5V. The SMPS2 output can be adjusted from 0.5V to 2.5V by setting REFIN2 voltage. This device features a linear regulator providing 3.3V/5V, or adjustable from 0.7V to 4.5V output via LDOREFIN. The linear regulator provides up to 100mA output current with automatic linear-regulator bootstrapping to the BYP input. When in switchover, the LDO output can source up to 200mA. The ISL6237 includes on-board power-up sequencing, power-good (POK_) outputs, digital soft-start, and internal soft-stop output discharge that prevents negative voltages on shutdown. Constant on-time PWM control scheme operates without sense resistors and provides 100ns response to load transients while maintaining a relatively constant switching frequency. The unique ultrasonic pulse-skipping mode maintains the switching frequency above 25kHz, which eliminates noise in audio applications. Other features include pulse skipping, which maximizes efficiency in light-load applications, and fixed-frequency PWM mode, which reduces RF interference in sensitive applications.
Features
* Wide Input Voltage Range 5.5V to 25V * Dual Fixed 1.05V/3.3V and 1.5V/5.0V Outputs or Adjustable 0.7V to 5.5V (SMPS1) and 0.5V to 2.5V (SMPS2), 1.5% Accuracy * 1.7ms Digital Soft-Start and Independent Shutdown * Fixed 3.3V/5.0V, or Adjustable Output 0.7V to 4.5V, 1.5% (LDO): 200mA * 2.0V Reference Voltage * Constant ON-TIME Control with 100ns Load-Step Response * Selectable Switching Frequency * rDS(ON) Current Sensing * Programmable Current Limit with Foldback Capability * Selectable PWM, Skip or Ultrasonic Mode * BOOT Voltage Monitor with Automatic Refresh * Independent POK1 and POK2 Comparators * Soft-Start with Pre-Biased Output and Soft-Stop * Independent ENABLE * High Efficiency - Up to 97% * Very High Light Load Efficiency (Skip Mode) * 5mW Quiescent Power Dissipation * Thermal Shutdown
Ordering Information
PART NUMBER ISL6237IRZ (Note) ISL6237IRZ-T (Note) PART MARKING TEMP. RANGE (C) PACKAGE (Pb-Free) PKG. DWG. #
* Extremely Low Components Count * Pb-Free Plus Anneal Available (RoHS Compliant)
ISL6237 IRZ -40 to +100 32 Ld 5x5 QFN L32.5x5B
Applications
ISL6237 IRZ -40 to +100 32 Ld 5x5 QFN L32.5x5B Tape and Reel
* Notebook and Sub-Notebook Computers * PDAs and Mobile Communication Devices * 3-Cell and 4-Cell Li+ Battery-Powered Devices * DDR1, DDR2, and DDR3 Power Supplies * Graphic Cards * Game Consoles * Telecommunication
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL6237 Pinout
ISL6237 (32 LD 5x5 QFN) TOP VIEW
PHASE2 25 24 BOOT2 23 LGATE2 22 PGND 21 GND 20 NC 19 PVCC 18 LGATE1 17 BOOT1 9 BYP 10 OUT1 11 FB1 12 ILIM1 13 POK1 14 EN1 15 UGATE1 16 PHASE1 UGATE2 26 REFIN2 SKIP# POK2 28 OUT2 ILIM2 EN2 27
32 REF TON VCC EN_LDO NC VIN LDO LDOREFIN 1 2 3 4 5 6 7 8
31
30
29
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FN6418.1 March 16, 2007
ISL6237
Absolute Voltage Ratings
VIN, EN_LDO to GND . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +27V BOOT_ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +33V BOOT_ to PHASE_ . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V VCC, EN_, SKIP#, TON, PVCC, POK_ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V LDO, FB1, REFIN2, LDOREFIN to GND . . . -0.3V to (VCC + 0.3V) OUT_, REF to GND . . . . . . . . . . . . . . . . . . . . -0.3V to (VCC + 0.3V UGATE_ to PHASE_ . . . . . . . . . . . . . . . . . . -0.3V to (PVCC + 0.3V) ILIM_ to GND . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VCC + 0.3V) LGATE_, BYP to GND . . . . . . . . . . . . . . . . . -0.3V to (PVCC + 0.3V) PGND to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to + 0.3V LDO, REF Short Circuit to GND . . . . . . . . . . . . . . . . . . . Continuous VCC Short Circuit to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1s LDO Current (Internal Regulator) Continuous . . . . . . . . . . . . 100mA LDO Current (Switched Over to OUT1) Continuous . . . . . . +200mA
Thermal Information
Thermal Resistance (Typical) JA (C/W) JC (CW) 32 Ld QFN (Notes 1, 2) . . . . . . . . . . . . 32 3.0 Operating Temperature Range . . . . . . . . . . . . . . . .-40C to +100C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150C Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C
CAUTION: Stress above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied.
NOTES: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 2. For JC, the "case temp" location is the center of the exposed metal pad on the package underside.
Electrical Specifications
PARAMETER MAIN SMPS CONTROLLERS VIN Input Voltage Range
No load on LDO, OUT1, OUT2, and REF, VIN = 12V, EN2 = EN1 = VCC, VBYP = 5V, PVCC = 5V, VEN_LDO = 5V, TA = -40C to +100C, unless otherwise noted. Typical values are at TA = +25C. CONDITIONS MIN TYP MAX UNITS
LDO in regulation VIN = LDO, VOUT1 < 4.43V
5.5 4.5 3.285 1.038 1.482 4.975 0.693 0.7 0.70 0.50 -1.0 -0.1 -1.7 -1.5 0.005 4.75 0.2 5 3.330 1.05 1.500 5.050 0.700
25 5.5 3.375 1.062 1.518 5.125 0.707 2.50 5.50 2.50 1.0
V V V V V V V V V V % % % % %/V
3.3V Output Voltage in Fixed Mode 1.05V Output Voltage in Fixed Mode 1.5V Output Voltage in Fixed Mode 5V Output Voltage in Fixed Mode FB1 in Output Adjustable Mode REFIN2 in Output Adjustable Mode SMPS1 Output Voltage Adjust Range SMPS2 Output Voltage Adjust Range SMPS2 Output Voltage Accuracy (Referred for REFIN2) DC Load Regulation
VIN = 5.5V to 25V, REFIN2 > (VCC - 1V), SKIP# = 5V VIN= 5.5V to 25V, 3.0 < REFIN2 < (VCC - 1.1V), SKIP# = 5V VIN = 5.5V to 25V, FB1 = VCC, SKIP# = 5V VIN = 5.5V to 25V, FB1 = GND, SKIP# = 5V VIN = 5.5V to 25V VIN = 5.5V to 25V SMPS1 SMPS2 REFIN2 = 0.7V to 2.5V, SKIP# = VCC Either SMPS, SKIP# = VCC, 0 to 5A Either SMPS, SKIP# = REF, 0 to 5A Either SMPS, SKIP# = GND, 0 to 5A
Line Regulation Current-Limit Current Source ILIM_ Adjustment Range Current-Limit Threshold (Positive, Default)
Either SMPS, 6V < VIN < 24V Temperature = +25C
5.25 2
A V mV
ILIM_ = VCC, GND - PHASE_ (No temperature compensation)
93
100
107
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FN6418.1 March 16, 2007
ISL6237
Electrical Specifications
PARAMETER Current-Limit Threshold (Positive, Adjustable) GND - PHASE_ No load on LDO, OUT1, OUT2, and REF, VIN = 12V, EN2 = EN1 = VCC, VBYP = 5V, PVCC = 5V, VEN_LDO = 5V, TA = -40C to +100C, unless otherwise noted. Typical values are at TA = +25C. (Continued) CONDITIONS VILIM_ = 0.5V VILIM_= 1V VILIM_ = 2V Zero-Current Threshold Current-Limit Threshold (Negative, Default) Soft-Start Ramp Time Operating Frequency SKIP# = GND, REF, or OPEN, GND - PHASE_ SKIP# = VCC, GND - PHASE_ Zero to full limit (VtON = GND), SKIP# = VCC SMPS 1 SMPS 2 (VtON = REF or OPEN), SKIP# = VCC (VtON = VCC), SKIP# = VCC SMPS 1 SMPS 2 SMPS 1 SMPS 2 On-Time Pulse Width VtON = GND (400kHz/500kHz) VOUT1 = 5.00V VOUT2 = 3.33V VtON = REF or OPEN (400kHz/300kHz) VtON = VCC (200kHz/300kHz) VOUT1 = 5.05V VOUT2 = 3.33V VOUT1 = 5.05V VOUT2 = 3.33V Minimum Off-Time Maximum Duty Cycle VtON = GND VOUT1 = 5.05V VOUT2 = 3.33V VtON = REF or OPEN VOUT1 = 5.05V VOUT2 = 3.33V VtON = VCC VOUT1 = 5.05V VOUT2 = 3.33V Ultrasonic SKIP Operating Frequency SKIP# = REF or OPEN 25 0.895 0.475 0.895 0.833 1.895 0.833 200 MIN 40 93 185 TYP 50 100 200 3 -120 1.7 400 500 400 300 200 300 1.052 0.555 1.052 0.925 2.105 0.925 300 88 85 88 91 94 91 37 1.209 0.635 1.209 1.017 2.315 1.017 400 MAX 60 107 215 UNITS mV mV mV mV mV ms kHz kHz kHz kHz kHz kHz s s s s s s ns % % % % % % kHz
INTERNAL REGULATOR AND REFERENCE LDO Output Voltage LDO Output Voltage LDO Output in Adjustable Mode LDO Output Accuracy in Adjustable Mode BYP = GND, 5.5V < VIN < 25V, LDOREFIN < 0.3V, 0 < ILDO < 100mA BYP = GND, 5.5V < VIN < 25V, LDOREFIN > (VCC - 1V), 0 < ILDO < 100mA VIN = 5.5V to 25V, VLDO = 2 x VLDOREFIN VIN = 5.5V to 25V, VLDOREFIN = 0.35V to 0.5V VIN = 5.5V to 25V, VLDOREFIN = 0.5V to 2.25V LDOREFIN Input Range LDO Output Current LDO Output Current During Switchover LDO Output Current During Switchover to 3.3V LDO Short-Circuit Current VLDO = 2 x VLDOREFIN BYP = GND, VIN = 5.5V to 25V, Guaranteed by design BYP = 5V, VIN = 5.5V to 25V, LDOREFIN < 0.3V BYP = 3.3V, VIN = 5.5V to 25V, LDOREFIN > (VCC - 1V) LDO = GND, BYP = GND 200 0.35 4.925 3.250 0.7 5.000 3.300 5.075 3.350 4.5 2.5 1.5 2.25 100 200 100 400 V V V % % V mA mA mA mA
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FN6418.1 March 16, 2007
ISL6237
Electrical Specifications
PARAMETER Undervoltage-Lockout Fault Threshold No load on LDO, OUT1, OUT2, and REF, VIN = 12V, EN2 = EN1 = VCC, VBYP = 5V, PVCC = 5V, VEN_LDO = 5V, TA = -40C to +100C, unless otherwise noted. Typical values are at TA = +25C. (Continued) CONDITIONS Rising edge of PVCC Falling edge of PVCC LDO 5V Bootstrap Switch Threshold to BYP Rising edge at BYP regulation point LDOREFIN = GND LDO 3.3V Bootstrap Switch Threshold to BYP LDO 5V Bootstrap Switch Equivalent Resistance LDO 3.3V Bootstrap Switch Equivalent Resistance REF Output Voltage REF Load Regulation REF Sink Current VIN Operating Supply Current VIN Standby Supply Current VIN Shutdown Supply Current Quiescent Power Consumption FAULT DETECTION Overvoltage Trip Threshold FB1 with respect to nominal regulation point REFIN2 with respect to nominal regulation point Overvoltage Fault Propagation Delay POK_ Threshold POK_ Propagation Delay POK_ Output Low Voltage POK_ Leakage Current Thermal-Shutdown Threshold Output Undervoltage Shutdown Threshold Output Undervoltage Shutdown Blanking Time INPUTS AND OUTPUTS FB1 Input Voltage Low level High level REFIN2 Input Voltage OUT2 Dynamic Range, VOUT2 = VREFIN2 Fixed OUT2 = 1.05V Fixed OUT2 = 3.3V LDOREFIN Input Voltage Fixed LDO = 5V LDO Dynamic Range, VLDO = 2 x VLDOREFIN Fixed LDO = 3.3V 0.35 VCC - 1.0 VCC - 1.0 0.5 3.0 VCC - 1.0 0.30 2.25 2.50 VCC - 1.1 0.3 V V V V V V V V FB1 or REFIN2 with respect to nominal output voltage From EN_ signal 65 10 FB1 or REFIN2 delay with 50mV overdrive FB1 or REFIN2 with respect to nominal output, falling edge, typical hysteresis = 1% Falling edge, 50mV overdrive ISINK = 4mA High state, forced to 5.5V +150 70 20 75 30 -12 +8 +12 +11 +16 10 -9 10 0.2 1 -6 +14 +20 % % s % s V A C % ms Rising edge at BYP regulation point LDOREFIN = VCC LDO to BYP, BYP = 5V, LDOREFIN > (VCC - 1V), Guaranteed by design LDO to BYP, BYP = 3.3V, LDOREFIN < 0.3V, Guaranteed by design No external load 0 < ILOAD < 50A REF in regulation Both SMPSs on, FB1 = SKIP# = GND, REFIN2 = VCC VOUT1 = BYP = 5.3V, VOUT2 = 3.5V VIN = 5.5V to 25V, both SMPSs off, EN_LDO = VCC VIN = 4.5V to 25V, EN1 = EN2 = EN_LDO = 0V Both SMPSs on, FB1 = SKIP# = GND, REFIN2 = VCC, VOUT1 = BYP = 5.3V, VOUT2 = 3.5V 10 25 180 20 5 50 250 30 7 1.980 3.9 4.53 3.0 MIN TYP 4.35 4.05 4.68 3.1 0.7 1.5 2.000 10 4.83 3.2 1.5 3.0 2.020 MAX 4.5 UNITS V V V V V mV A A A A mW
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FN6418.1 March 16, 2007
ISL6237
Electrical Specifications
PARAMETER SKIP# Input Voltage Low level (SKIP) Float level (ULTRASONIC SKIP) High level (PWM) TON Input Voltage Low level Float level High level EN1, EN2 Input Voltage Clear fault level/SMPS off level Delay start level SMPS on level EN_LDO Input Voltage Rising edge Falling edge Input Leakage Current VtON = 0 or 5V VEN_ = VEN_LDO = 0V or 5V VSKIP# = 0V or 5V VFB1 = 0V or 5V VREFIN = 0V or 2.5V VLDOREFIN = 0V or 2.75V INTERNAL BOOT DIODE VD Forward Voltage IBOOT_LEAKAGE Leakage Current MOSFET DRIVERS UGATE_ Gate-Driver Sink/Source Current LGATE_ Gate-Driver Source Current LGATE_ Gate-Driver Sink Current UGATE_ Gate-Driver On-Resistance LGATE_ Gate-Driver On-Resistance UGATE1, UGATE2 forced to 2V LGATE1 (source), LGATE2 (source), forced to 2V LGATE1 (sink), LGATE2 (sink), forced to 2V BST_ - PHASE_ forced to 5V, Guaranteed by design LGATE_, high state (pull-up), Guaranteed by design LGATE_, low state (pull-down), Guaranteed by design Dead Time LGATE_ Rising UGATE_ Rising OUT1, OUT2 Discharge On Resistance 15 20 2 1.7 3.3 1.5 2.2 0.6 20 30 25 4.0 5.0 1.5 35 50 40 A A A ns ns PVCC - VBOOT, IF = 10mA VBOOT = 30V, PHASE = 25V, PVCC = 5V 0.65 0.8 500 V nA 1.7 2.4 1.2 0.94 -1 -0.1 -1 -0.2 -0.2 -0.2 1.6 1.00 2.0 1.06 +1 +0.1 +1 +0.2 +0.2 +0.2 1.7 2.4 0.8 2.3 1.7 2.4 0.8 2.3 No load on LDO, OUT1, OUT2, and REF, VIN = 12V, EN2 = EN1 = VCC, VBYP = 5V, PVCC = 5V, VEN_LDO = 5V, TA = -40C to +100C, unless otherwise noted. Typical values are at TA = +25C. (Continued) CONDITIONS MIN TYP MAX 0.8 2.3 UNITS V V V V V V V V V V V A A A A A A
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FN6418.1 March 16, 2007
ISL6237 Pin Descriptions
PIN 1 2 NAME REF TON FUNCTION 2V Reference Output. Bypass to GND with a 0.1F (min) capacitor. REF can source up to 50A for external loads. Loading REF degrades FB and output accuracy according to the REF load-regulation error. Frequency Select Input. Connect to GND for 400kHz/500kHz operation. Connect to REF (or leave OPEN) for 400kHz/300kHz operation. Connect to VCC for 200kHz/300kHz operation (5V/3.3V SMPS switching frequencies, respectively.) Analog Supply Voltage Input for PWM Core. Bypass to GND with a 1F ceramic capacitor. LDO Enable Input. The LDO is enabled if EN_LDO is within logic high level and disabled if EN_LDO is less than the logic low level. No connect. Power-Supply Input. VIN is used for the constant-on-time PWM on-time one-shot circuits. VIN is also used to power the linear regulators. The linear regulators are powered by SMPS1 if OUT1 is set greater than 4.78V and BYP is tied to OUT1. Connect VIN to the battery input and bypass with a 1F capacitor. Linear-Regulator Output. LDO can provide a total of 100mA external loads. The LDO regulate at 5V If LDOREFIN is connected to GND. When the LDO is set at 5V and BYP is within 5V switchover threshold, the internal regulator shuts down and the LDO output pin connects to BYP through a 0.7 switch. The LDO regulate at 3.3V if LDOREFIN is connected to VCC. When the LDO is set at 3.3V and BYP is within 3.3V switchover threshold, the internal regulator shuts down and the LDO output pin connects to BYP through a 1.5 switch. Bypass LDO output with a minimum of 4.7F ceramic.
3 4 5 6
VCC EN_LDO NC VIN
7
LDO
8
LDOREFIN LDO Reference Input. Connect LDOREFIN to GND for fixed 5V operation. Connect LDOREFIN to VCC for fixed 3.3V operation. LDOREFIN can be used to program LDO output voltage from 0.7V to 4.5V. LDO output is two times the voltage of LDOREFIN. There is no switchover in adjustable mode. BYP OUT1 FB1 ILIM1 BYP is the switchover source voltage for the LDO when LDOREFIN connected to GND or VCC. Connect BYP to 5V if LDOREFIN is tied GND. Connect BYP to 3.3V if LDOREFIN is tied to VCC. SMPS1 Output Voltage-Sense Input. Connect to the SMPS1 output. OUT1 is an input to the Constant on-time-PWM on-time one-shot circuit. It also serves as the SMPS1 feedback input in fixed-voltage mode. SMPS1 Feedback Input. Connect FB1 to GND for fixed 5V operation. Connect FB1 to VCC for fixed 1.5V operation Connect FB1 to a resistive voltage-divider from OUT1 to GND to adjust the output from 0.7V to 5.5V. SMPS1 Current-Limit Adjustment. The GND-PHASE1 current-limit threshold is 1/10th the voltage seen at ILIM1 over a 0.2V to 2V range. There is an internal 5A current source from VCC to ILIM1. Connect ILIM1 to REF for a fixed 200mV threshold. The logic current limit threshold is default to 100mV value if ILIM1 is higher than VCC - 1V. SMPS1 Power-Good Open-Drain Output. POK1 is low when the SMPS1 output voltage is more than 10% below the normal regulation point or during soft-start. POK1 is high impedance when the output is in regulation and the soft-start circuit has terminated. POK1 is low in shutdown. SMPS1 Enable Input. The SMPS1 is enabled if EN1 is greater than the logic high level and disabled if EN1 is less than the logic low level. If EN1 is connected to REF, the SMPS1 starts after the SMPS2 reaches regulation (delay start). Drive EN1 below 0.8V to clear fault level and reset the fault latches. High-Side MOSFET Floating Gate-Driver Output for SMPS1. UGATE1 swings between PHASE1 and BOOT1. Inductor Connection for SMPS1. PHASE1 is the internal lower supply rail for the UGATE1 high-side gate driver. PHASE1 is the current-sense input for the SMPS1. Boost Flying Capacitor Connection for SMPS1. Connect to an external capacitor according to the typical application circuits (Figure 62 and Figure 63). See "MOSFET Gate Drivers (UGATE_, LGATE_)" on page 27. SMPS1 Synchronous-Rectifier Gate-Drive Output. LGATE1 swings between GND and PVCC. PVCC is the supply voltage for the low-side MOSFET driver LGATE_. Connect a 5V power source to the PVCC pin (bypass with 1F MLCC capacitor to PGND if necessary). There is internal 10 connecting PVCC to VCC. Make sure that both VCC and PVCC are bypassed with 1F MLCC capacitors. No connect. Analog Ground for both SMPS_ and LDO. Connect externally to the underside of the exposed pad. Power Ground for SMPS_ controller. Connect PGND externally to the underside of the exposed pad. SMPS2 Synchronous-Rectifier Gate-Drive Output. LGATE2 swings between GND and PVCC.
9 10 11 12
13
POK1
14
EN1
15 16 17 18 19
UGATE1 PHASE1 BOOT1 LGATE1 PVCC
20 21 22 23
NC GND PGND LGATE2
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FN6418.1 March 16, 2007
ISL6237 Pin Descriptions (Continued)
PIN 24 25 26 27 NAME BOOT2 PHASE2 UGATE2 EN2 FUNCTION Boost Flying Capacitor Connection for SMPS2. Connect to an external capacitor according to the typical application circuits (Figure 62 and Figure 63). See "MOSFET Gate Drivers (UGATE_, LGATE_)" on page 27. Inductor Connection for SMPS2. PHASE2 is the internal lower supply rail for the UGATE2 high-side gate driver. PHASE2 is the current-sense input for the SMPS2. High-Side MOSFET Floating Gate-Driver Output for SMPS2. UGATE1 swings between PHASE2 and BOOT2. SMPS2 Enable Input. The SMPS2 is enabled if EN2 is greater than the logic high level and disabled if EN2 is less than the logic low level. If EN2 is connected to REF, the SMPS2 starts after the SMPS1 reaches regulation (delay start). Drive EN2 below 0.8V to clear fault level and reset the fault latches. SMP2 Power-Good Open-Drain Output. POK2 is low when the SMPS2 output voltage is more than 10% below the normal regulation point or during soft-start. POK2 is high impedance when the output is in regulation and the soft-start circuit has terminated. POK2 is low in shutdown. Low-Noise Mode Control. Connect SKIP# to GND for normal Idle-Mode (pulse-skipping) operation or to VCC for PWM mode (fixed frequency). Connect to REF or leave floating for ultrasonic skip mode operation. SMPS2 Output Voltage-Sense Input. Connect to the SMPS2 output. OUT2 is an input to the Constant on-time-PWM on-time one-shot circuit. It also serves as the SMPS2 feedback input in fixed-voltage mode. SMPS2 Current-Limit Adjustment. The GND-PHASE1 current-limit threshold is 1/10th the voltage seen at ILIM2 over a 0.2V to 2V range. There is an internal 5A current source from VCC to ILIM2. Connect ILIM2 to REF for a fixed 200mV. The logic current limit threshold is default to 100mV value if ILIM2 is higher than VCC - 1V. Output voltage control for SMPS2. Connect REFIN2 to VCC for fixed 3.3V. Connect REFIN2 to a 3.3V supply for fixed 1.05V. REFIN2 can be used to program SMPS2 output voltage from 0.5V to 2.50V. SMPS2 output voltage is 0V if REFIN2 < 0.5V.
28
POK2
29 30 31
SKIP# OUT2 ILIM2
32
REFIN2
Typical Performance Curves
Circuit of Figure 62 and Figure 63, no load on LDO, OUT1, OUT2, and REF, VIN = 12V, EN2 = EN1 = VCC, VBYP = 5V, PVCC = 5V, VEN_LDO = 5V, TA = -40C to +100C, unless otherwise noted. Typical values are at TA = +25C.
7 VIN SKIP MODE 7 VIN PWM MODE 7 VIN ULTRA SKIP MODE 12 VIN SKIP MODE 12 VIN PWM MODE 12 VIN ULTRA SKIP MODE 25 VIN SKIP MODE 25 VIN PWM MODE 25 VIN ULTRA SKIP MODE
7 VIN SKIP MODE 7 VIN PWM MODE 7 VIN ULTRA SKIP MODE 12 VIN SKIP MODE 12 VIN PWM MODE 100 90 80 EFFICIENCY (%)
12 VIN ULTRA SKIP MODE 25 VIN SKIP MODE 25 VIN PWM MODE 25 VIN ULTRA SKIP MODE 100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 0.001
70 60 50 40 30 20 10 0 0.001 0.010 0.100 OUTPUT LOAD (A) 1.000 10.000
0.010
0.100 OUTPUT LOAD (A)
1.000
10.000
FIGURE 1. VOUT2 = 1.05V EFFICIENCY vs LOAD (300kHz)
FIGURE 2. VOUT1 = 1.5V EFFICIENCY vs LOAD (200kHz)
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FN6418.1 March 16, 2007
ISL6237 Typical Performance Curves
Circuit of Figure 62 and Figure 63, no load on LDO, OUT1, OUT2, and REF, VIN = 12V, EN2 = EN1 = VCC, VBYP = 5V, PVCC = 5V, VEN_LDO = 5V, TA = -40C to +100C, unless otherwise noted. Typical values are at TA = +25C. (Continued)
7 VIN SKIP MODE 7 VIN PWM MODE 7 VIN ULTRA SKIP MODE 12 VIN SKIP MODE 12 VIN PWM MODE 12 VIN ULTRA SKIP MODE 25 VIN SKIP MODE 25 VIN PWM MODE 25 VIN ULTRA SKIP MODE
100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 0.001
7 VIN SKIP MODE 7 VIN PWM MODE 7 VIN ULTRA SKIP MODE 12 VIN SKIP MODE 12 VIN PWM MODE
12 VIN ULTRA SKIP MODE 25 VIN SKIP MODE 25 VIN PWM MODE 25 VIN ULTRA SKIP MODE 100 90 EFFICIENCY (%) 80 70 60 50 40 30 20 10
0.010
0.100 OUTPUT LOAD (A)
1.000
10.000
0 0.001
0.010
0.100 OUTPUT LOAD (A)
1.000
10.000
FIGURE 3. VOUT2 = 3.3V EFFICIENCY vs LOAD (500kHz)
7 VIN SKIP MODE 7 VIN PWM MODE 7 VIN ULTRA SKIP MODE 12 VIN SKIP MODE 12 VIN PWM MODE 12 VIN ULTRA SKIP MODE 25 VIN SKIP MODE 25 VIN PWM MODE 25 VIN ULTRA SKIP MODE
FIGURE 4. VOUT1 = 5V EFFICIENCY vs LOAD (400kHz)
7 VIN SKIP MODE 7 VIN PWM MODE 7 VIN ULTRA SKIP MODE 12 VIN SKIP MODE 12 VIN PWM MODE 12 VIN ULTRA SKIP MODE 25 VIN SKIP MODE 25 VIN PWM MODE 25 VIN ULTRA SKIP MODE
1.070 1.068 OUTPUT VOLTAGE (V)
1.540 1.535 OUTPUT VOLTAGE (V) 1.530 1.525 1.520 1.515 1.510 1.505
1.066 1.064 1.062 1.060 1.058 1.056 1.054 1.052 1.050 0.001 0.010 0.100 OUTPUT LOAD (A) 1.000 10.000
1.500 0.001
0.010
0.100 OUTPUT LOAD (A)
1.000
10.000
FIGURE 5. VOUT2 = 1.05V REGULATION vs LOAD (300kHz)
7 VIN SKIP MODE 7 VIN PWM MODE 7 VIN ULTRA SKIP MODE 12 VIN SKIP MODE 12 VIN PWM MODE 12 VIN ULTRA SKIP MODE 25 VIN SKIP MODE 25 VIN PWM MODE 25 VIN ULTRA SKIP MODE
FIGURE 6. VOUT1 = 1.5V REGULATION vs LOAD (200kHz)
7 VIN SKIP MODE 7 VIN PWM MODE 7 VIN ULTRA SKIP MODE 12 VIN SKIP MODE 12 VIN PWM MODE 12 VIN ULTRA SKIP MODE 25 VIN SKIP MODE 25 VIN PWM MODE 25 VIN ULTRA SKIP MODE
3.380 3.370
5.160 5.140 OUTPUT VOLTAGE (V) 5.120 5.100 5.080 5.060 5.040 5.020
OUTPUT VOLTAGE (V)
3.360 3.350 3.340 3.330 3.320 3.310 0.001
0.010
0.100 OUTPUT LOAD (A)
1.000
10.000
5.000 0.001
0.010
0.100 OUTPUT LOAD (A)
1.000
10.000
FIGURE 7. VOUT2 = 3.3V REGULATION vs LOAD (500kHz)
FIGURE 8. VOUT1 = 5V REGULATION vs LOAD (400kHz)
9
FN6418.1 March 16, 2007
ISL6237 Typical Performance Curves
Circuit of Figure 62 and Figure 63, no load on LDO, OUT1, OUT2, and REF, VIN = 12V, EN2 = EN1 = VCC, VBYP = 5V, PVCC = 5V, VEN_LDO = 5V, TA = -40C to +100C, unless otherwise noted. Typical values are at TA = +25C. (Continued)
7 VIN SKIP MODE 7 VIN PWM MODE 7 VIN ULTRA SKIP MODE 12 VIN SKIP MODE 12 VIN PWM MODE 12 VIN ULTRA SKIP MODE 25 VIN SKIP MODE 25 VIN PWM MODE 25 VIN ULTRA SKIP MODE
2.5 POWER DISSIPATION (W)
7 VIN SKIP MODE 7 VIN PWM MODE 7 VIN ULTRA SKIP MODE 12 VIN SKIP MODE 12 VIN PWM MODE
12 VIN ULTRA SKIP MODE 25 VIN SKIP MODE 25 VIN PWM MODE 25 VIN ULTRA SKIP MODE 2.5 POWER DISSIPATION (W)
2.0
2.0
1.5
1.5
1.0
1.0
0.5
0.5
0 0.001
0.010
0.100 OUTPUT LOAD (A)
1.000
10.000
0 0.001
0.010
0.100 OUTPUT LOAD (A)
1.000
10.000
FIGURE 9. VOUT2 = 1.05V POWER DISSIPATION vs LOAD (300kHz)
7 VIN SKIP MODE 7 VIN PWM MODE 7 VIN ULTRA SKIP MODE 12 VIN SKIP MODE 12 VIN PWM MODE 12 VIN ULTRA SKIP MODE 25 VIN SKIP MODE 25 VIN PWM MODE 25 VIN ULTRA SKIP MODE
FIGURE 10. VOUT1 = 1.5V POWER DISSIPATION vs LOAD (200kHz)
7 VIN SKIP MODE 7 VIN PWM MODE 7 VIN ULTRA SKIP MODE 12 VIN SKIP MODE 12 VIN PWM MODE 12 VIN ULTRA SKIP MODE 25 VIN SKIP MODE 25 VIN PWM MODE 25 VIN ULTRA SKIP MODE
3.5 POWER DISSIPATION (W) 3.0 2.5 2.0 1.5 1.0 0.5
3.5 POWER DISSIPATION (W) 3.0 2.5 2.0 1.5 1.0 0.5 0
0 0.001
0.010
0.100 OUTPUT LOAD (A)
1.000
10.000
0.001
0.010
0.100 OUTPUT LOAD (A)
1.000
10.000
FIGURE 11. VOUT2 = 3.3V POWER DISSIPATION vs LOAD (500kHz)
FIGURE 12. VOUT1 = 5V POWER DISSIPATION vs LOAD (400kHz)
1.064 NO LOAD PWM 1.062 OUTPUT VOLTAGE (V) 1.060 1.058 1.056 1.054 1.052 MAX LOAD PWM 1.050 1.048 5 7 9 11 13 15 17 19 21 23 25 INPUT VOLTAGE (V) MID LOAD PWM OUTPUT VOLTAGE (V)
1.068 1.066 1.064 1.062 1.060 1.058 1.056 1.054 1.052 1.050 1.048 5 7 9 11 13 15 17 19 INPUT VOLTAGE (V) 21 23 25 MAX LOAD PWM MAX LOAD PWM MID LOAD PWM NO LOAD PWM
FIGURE 13. VOUT2 = 1.05V OUTPUT VOLTAGE REGULATION vs VIN (PWM MODE)
FIGURE 14. VOUT2 = 1.05V OUTPUT VOLTAGE REGULATION vs VIN (SKIP MODE)
10
FN6418.1 March 16, 2007
ISL6237 Typical Performance Curves
Circuit of Figure 62 and Figure 63, no load on LDO, OUT1, OUT2, and REF, VIN = 12V, EN2 = EN1 = VCC, VBYP = 5V, PVCC = 5V, VEN_LDO = 5V, TA = -40C to +100C, unless otherwise noted. Typical values are at TA = +25C. (Continued)
1.530 1.525 OUTPUT VOLTAGE (V) NO LOAD PWM NO LOAD PWM 1.520 MID LOAD PWM 1.515 1.510 MAX LOAD PWM 1.505 1.500 5 7 9 11 13 15 17 19 INPUT VOLTAGE (V) 21 23 25 5 7 9 11 13 15 17 19 INPUT VOLTAGE (V) 21 23 25
1.518 1.516 OUTPUT VOLTAGE (V) 1.514 1.512 MID LOAD PWM 1.510 1.508 1.506 1.504 MAX LOAD PWM
FIGURE 15. VOUT1 = 1.5V OUTPUT VOLTAGE REGULATION vs VIN (PWM MODE)
FIGURE 16. VOUT1 = 1.5V OUTPUT VOLTAGE REGULATION vs VIN (SKIP MODE)
3.340 3.335 OUTPUT VOLTAGE (V) 3.330 3.325 3.320 3.315 MAX LOAD PWM 3.310 7 9 11 13 15 17 19 INPUT VOLTAGE (V) 21 23 25 MID LOAD PWM NO LOAD PWM
3.380 3.370 OUTPUT VOLTAGE (V) 3.360 3.350 3.340 3.330 3.320 3.310 3.300 7 9 11 13 15 17 19 INPUT VOLTAGE (V) 21 23 25 MID LOAD PWM MAX LOAD PWM NO LOAD PWM
FIGURE 17. VOUT2 = 3.3V OUTPUT VOLTAGE REGULATION vs VIN (PWM MODE)
FIGURE 18. VOUT2 = 3.3V OUTPUT VOLTAGE REGULATION vs VIN (SKIP MODE)
5.065 NO LOAD PWM OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 5.060 MAX LOAD PWM MID LOAD PWM 5.050 5.140 5.120 5.100 5.080 MID LOAD PWM 5.060 5.040 5.020 MAX LOAD PWM 7 9 11 13 15 17 19 21 23 25 INPUT VOLTAGE (V) NO LOAD PWM
5.055
5.045
5.040 7 9 11 13 15 17 19 INPUT VOLTAGE (V) 21 23 25
FIGURE 19. VOUT1 = 5V OUTPUT VOLTAGE REGULATION vs VIN (PWM MODE)
FIGURE 20. VOUT1 = 5V OUTPUT VOLTAGE REGULATION vs VIN (SKIP MODE)
11
FN6418.1 March 16, 2007
ISL6237 Typical Performance Curves
Circuit of Figure 62 and Figure 63, no load on LDO, OUT1, OUT2, and REF, VIN = 12V, EN2 = EN1 = VCC, VBYP = 5V, PVCC = 5V, VEN_LDO = 5V, TA = -40C to +100C, unless otherwise noted. Typical values are at TA = +25C. (Continued)
50 45 250 FREQUENCY (kHz) RIPPLE (mV) 200 PWM 150 100 50 SKIP 0 0.001 0.010 0.100 OUTPUT LOAD (A) 1.000 10.000 40 35 30 25 20 15 10 5 0 0.001 0.010 0.100 OUTPUT LOAD (A) SKIP 1.000 10.000 PWM ULTRA-SKIP
300
ULTRA-SKIP
FIGURE 21. VOUT2 = 1.05V FREQUENCY vs LOAD
FIGURE 22. VOUT2 = 1.05V RIPPLE vs LOAD
250 PWM 200 FREQUENCY (kHz) RIPPLE (mV)
50 45 40 35 PWM
150
30 25 20 ULTRA-SKIP 15 10 SKIP
100 ULTRA-SKIP 50 SKIP 0 0.001 0.010 0.100 OUTPUT LOAD (A) 1.000 10.000
5 0 0.001 0.010 0.100 OUTPUT LOAD (A) 1.000 10.000
FIGURE 23. VOUT1 = 1.5V FREQUENCY vs LOAD
FIGURE 24. VOUT1 = 1.5V RIPPLE vs LOAD
600 PWM 500 FREQUENCY (kHz) 400 300 200 100
14 PWM 12 10 RIPPLE (mV) 8 6 4 2 0 0.001 0.010 0.100 OUTPUT LOAD (A) 1.000 10.000 ULTRA-SKIP SKIP
ULTRA-SKIP SKIP 0.010 0.100 OUTPUT LOAD (A) 1.000 10.000
0 0.001
FIGURE 25. VOUT2 = 3.3V FREQUENCY vs LOAD
FIGURE 26. VOUT2 = 3.3V RIPPLE vs LOAD
12
FN6418.1 March 16, 2007
ISL6237 Typical Performance Curves
Circuit of Figure 62 and Figure 63, no load on LDO, OUT1, OUT2, and REF, VIN = 12V, EN2 = EN1 = VCC, VBYP = 5V, PVCC = 5V, VEN_LDO = 5V, TA = -40C to +100C, unless otherwise noted. Typical values are at TA = +25C. (Continued)
40 PWM 35 PWM 30 RIPPLE (mV) 25 20 15 10 5 SKIP 0.010 0.100 OUTPUT LOAD (A) 1.000 10.000 0 0.001 0.010 0.100 OUTPUT LOAD (A) 1.000 10.000 ULTRA-SKIP
450 400 FREQUENCY (kHz) 350 300 250 200 150 100 50 0 0.001 ULTRA-SKIP
SKIP
FIGURE 27. VOUT1 = 5V FREQUENCY vs LOAD
FIGURE 28. VOUT1 = 5V RIPPLE vs LOAD
5.04 5.02 OUTPUT VOLTAGE (V) 5.00 4.98 4.96 4.94 4.92 4.90 4.88 4.86 4.84 0 50 100 OUTPUT LOAD (mA) 150 200 BYP = 5V BYP = 0V OUTPUT VOLTAGE (V)
3.35 3.30 3.25 BYP = 0V 3.20 3.15 3.10 3.05 3.00 0 50 100 OUTPUT LOAD (mA) 150 200 BYP = 3.3V
FIGURE 29. LDO OUTPUT 5V vs LOAD
FIGURE 30. LDO OUTPUT 3.3V vs LOAD
50 45 INPUT CURRENT (mA) INPUT CURRENT (A) 7 9 11 13 15 17 19 INPUT VOLTAGE (V) 21 23 25 40 35 30 25 20
1400 1200 1000 800 600 400 200 0.0 7 9 11 13 15 17 19 INPUT VOLTAGE (V) 21 23 25
FIGURE 31. PWM NO LOAD INPUT CURRENT vs VIN (EN = EN2 = EN_LDO = VCC)
FIGURE 32. SKIP NO LOAD INPUT CURRENT vs VIN (EN1 = EN2 = EN_LDO = VCC)
13
FN6418.1 March 16, 2007
ISL6237 Typical Performance Curves
Circuit of Figure 62 and Figure 63, no load on LDO, OUT1, OUT2, and REF, VIN = 12V, EN2 = EN1 = VCC, VBYP = 5V, PVCC = 5V, VEN_LDO = 5V, TA = -40C to +100C, unless otherwise noted. Typical values are at TA = +25C. (Continued)
26.5 26.0 INPUT CURRENT (A) 25.5 25.0 24.5 24.0 23.5 23.0 22.5 22.0 7 9 11 13 15 17 19 INPUT VOLTAGE (V) 21 23 25 7 9 11 13 15 17 19 INPUT VOLTAGE (V) 21 23 25
177.5 177.0 INPUT CURRENT (A) 176.5 176.0 175.5 175.0 174.5 174.0 173.5 173.0
FIGURE 33. STANDBY INPUT CURRENT vs VIN (EN = EN2 = 0, EN_LDO = VCC)
FIGURE 34. SHUTDOWN INPUT CURRENT vs VIN (EN = EN2 = EN_LDO = 0)
EN1 5V/DIV VOUT1 2V/DIV
IL1 2A/DIV POK1 2V/DIV
FIGURE 35. START-UP VOUT1 = 5V (NO LOAD, SKIP MODE)
EN1 5V/DIV
EN1 5V/DIV VOUT1 2V/DIV
VOUT1 2V/DIV
IL1 2A/DIV
IL1 5A/DIV
POK1 2V/DIV
POK1 2V/DIV
FIGURE 36. START-UP VOUT1 = 5V (NO LOAD, PWM MODE)
FIGURE 37. START-UP VOUT1 = 5V (FULL LOAD, PWM MODE)
14
FN6418.1 March 16, 2007
ISL6237 Typical Performance Curves
Circuit of Figure 62 and Figure 63, no load on LDO, OUT1, OUT2, and REF, VIN = 12V, EN2 = EN1 = VCC, VBYP = 5V, PVCC = 5V, VEN_LDO = 5V, TA = -40C to +100C, unless otherwise noted. Typical values are at TA = +25C. (Continued)
EN2 5V/DIV VOUT2 2V/DIV IL2 2A/DIV
EN2 5V/DIV VOUT2 2V/DIV
IL2 2A/DIV POK2 2V/DIV POK2 2V/DIV
FIGURE 38. START-UP VOUT2 = 3.3V (NO LOAD, SKIP MODE)
FIGURE 39. START-UP VOUT1 = 3.3V (NO LOAD, PWM MODE)
EN2 5V/DIV EN2 5V/DIV VOUT2 2V/DIV VOUT2 2V/DIV VOUT1 2V/DIV
IL2 5A/DIV POK2 2V/DIV
POK2 5V/DIV POK1 5V/DIV
FIGURE 40. START-UP VOUT1 = 3.3V (FULL LOAD, PWM MODE)
FIGURE 41. DELAYED START-UP (VOUT1 = 5V, VOUT2 = 3.3V, EN1 = REF)
EN1 5V/DIV EN1 5V/DIV VOUT2 2V/DIV VOUT1 2V/DIV VOUT2 2V/DIV
POK1 5V/DIV POK2 5V/DIV
VOUT1 2V/DIV POK1 OR POK2 5V/DIV
FIGURE 42. DELAYED START-UP (VOUT1 = 5V, VOUT2 = 3.3V, EN2 = REF)
FIGURE 43. SHUTDOWN (VOUT1 = 5V, VOUT2 = 3.3V, EN2 = REF)
15
FN6418.1 March 16, 2007
ISL6237 Typical Performance Curves
Circuit of Figure 62 and Figure 63, no load on LDO, OUT1, OUT2, and REF, VIN = 12V, EN2 = EN1 = VCC, VBYP = 5V, PVCC = 5V, VEN_LDO = 5V, TA = -40C to +100C, unless otherwise noted. Typical values are at TA = +25C. (Continued)
LGATE1 5V/DIV
LGATE1 5V/DIV
VOUT1 RIPPLE 50mV/DIV VOUT1 RIPPLE 100mV/DIV
IL1 5A/DIV
IL1 5A/DIV
VOUT2 RIPPLE 50mV/DIV
VOUT2 RIPPLE 50mV/DIV
FIGURE 44. LOAD TRANSIENT VOUT1 = 5V
FIGURE 45. LOAD TRANSIENT VOUT1 = 5V (SKIP)
LGATE1 5V/DIV
LGATE2 5V/DIV
VOUT1 RIPPLE 20mV/DIV IL2 5A/DIV VOUT1 RIPPLE 20mV/DIV IL2 5A/DIV VOUT2 RIPPLE 50mV/DIV
VOUT2 RIPPLE 50mV/DIV
FIGURE 46. LOAD TRANSIENT VOUT1 = 3.3V (PWM)
FIGURE 47. LOAD TRANSIENT VOUT1 = 3.3V (SKIP)
VOUT RIPPLE 20mV/DIV EN1 5V/DIV LDO 1V/DIV VOUT1 0.5V/DIV
LDOREFIN 0.5V/DIV
IL1 2A/DIV
VOUT2 RIPPLE 50mV/DIV
POK1 2V/DIV
FIGURE 48. LDO TRACKING TO LDOREFIN
FIGURE 49. START-UP VOUT1 = 1.5V (NO LOAD, SKIP MODE)
16
FN6418.1 March 16, 2007
ISL6237 Typical Performance Curves
Circuit of Figure 62 and Figure 63, no load on LDO, OUT1, OUT2, and REF, VIN = 12V, EN2 = EN1 = VCC, VBYP = 5V, PVCC = 5V, VEN_LDO = 5V, TA = -40C to +100C, unless otherwise noted. Typical values are at TA = +25C. (Continued)
EN1 5V/DIV VOUT1 0.5V/DIV
EN1 5V/DIV VOUT1 0.5V/DIV
IL1 5A/DIV IL1 2A/DIV
POK1 2V/DIV
POK1 2V/DIV
FIGURE 50. START-UP VOUT1 = 1.5V (NO LOAD, PWM MODE)S
FIGURE 51. START-UP VOUT1 = 1.5V (FULL LOAD, PWM MODE)
EN2 5V/DIV VOUT2 0.5V/DIV
EN2 5V/DIV VOUT2 0.5V/DIV
IL2 2A/DIV
IL2 2A/DIV
POK2 2V/DIV
POK2 2V/DIV
FIGURE 52. START-UP VOUT2 = 1.05V (NO LOAD, SKIP MODE)
FIGURE 53. START-UP VOUT1 = 1.05V (NO LOAD, PWM MODE)
EN2 5V/DIV
VOUT2 0.5V/DIV
EN2 5V/DIV
VOUT2 0.5V/DIV IL2 2A/DIV VOUT1 2V/DIV
POK2 5V/DIV POK2 2V/DIV POK1 5V/DIV
FIGURE 54. START-UP VOUT1 = 1.05V (FULL LOAD, PWM MODE)
FIGURE 55. DELAYED START-UP (VOUT1 = 1.5V, VOUT2 = 1.05V, EN1 = REF)
17
FN6418.1 March 16, 2007
ISL6237 Typical Performance Curves
Circuit of Figure 62 and Figure 63, no load on LDO, OUT1, OUT2, and REF, VIN = 12V, EN2 = EN1 = VCC, VBYP = 5V, PVCC = 5V, VEN_LDO = 5V, TA = -40C to +100C, unless otherwise noted. Typical values are at TA = +25C. (Continued)
VOUT1 2V/DIV EN1 5V/DIV EN1 500mV/DIV VOUT2 2V/DIV VOUT2 500mV/DIV VOUT1 2V/DIV POK1 5V/DIV POK2 5V/DIV POK1 OR POK2 5V/DIV
FIGURE 56. DELAYED START-UP (VOUT1 = 1.5V, VOUT2 = 1.05V, EN2 = REF)
FIGURE 57. SHUTDOWN (VOUT1 = 1.5V, VOUT2 = 1.05V, EN2 = REF)
LGATE1 5V/DIV
LGATE1 5V/DIV
VOUT1 RIPPLE 50mV/DIV
VOUT1 RIPPLE 50mV/DIV
IL1 5A/DIV
IL1 5A/DIV
VOUT2 RIPPLE 20mV/DIV
VOUT2 RIPPLE 20mV/DIV
FIGURE 58. LOAD TRANSIENT VOUT1 = 1.5V (PWM)
FIGURE 59. LOAD TRANSIENT VOUT1 = 1.5V (SKIP)
LGATE2 5V/DIV
LGATE2 5V/DIV
VOUT1 RIPPLE 20mV/DIV
VOUT1 RIPPLE 20mV/DIV
IL2 5A/DIV IL1 5A/DIV VOUT2 RIPPLE 20mV/DIV
VOUT2 RIPPLE 20mV/DIV
FIGURE 60. LOAD TRANSIENT VOUT1 = 1.05V (PWM)
FIGURE 61. LOAD TRANSIENT VOUT1 = 1.05V (SKIP)
18
FN6418.1 March 16, 2007
ISL6237 Typical Application Circuits
The typical application circuits (Figures 62 and 63) generate the typical 5V/7A, 3.3V/11A, 1.25V/5A, static voltage/10A, 1.5V/5A, and 1.05V/5A supplies found in a notebook computer. The input supply range is 5.5V to 25V.
5V 3.3V 2 x LDOREFIN TABLE 1. LDO OUTPUT VOLTAGE TABLE (Continued) LDO VOLTAGE CONDITIONS LDOREFIN < 0.3V, BYP < 4.63V LDOREFIN > VCC - 1V, BYP < 3V 0.35V < LDOREFIN < 2.25V COMMENT Internal LDO is active. Internal LDO is active. Internal LDO is active.
Detailed Description
The ISL6237 dual-buck, BiCMOS, switch-mode powersupply controller generates logic supply voltages for notebook computers. The ISL6237 is designed primarily for battery-powered applications where high efficiency and lowquiescent supply current are critical. The ISL6237 provides a pin-selectable switching frequency, allowing operation for 200kHz/300kHz, 400kHz/300kHz, or 400kHz/500kHz on the SMPSs. Light-load efficiency is enhanced by automatic Idle-Mode operation, a variable-frequency pulse-skipping mode that reduces transition and gate-charge losses. Each step-down, power-switching circuit consists of two N-Channel MOSFETs, a rectifier, and an LC output filter. The output voltage is the average AC voltage at the switching node, which is regulated by changing the duty cycle of the MOSFET switches. The gate-drive signal to the N-Channel high-side MOSFET must exceed the battery voltage, and is provided by a flying-capacitor boost circuit that uses a 100nF capacitor connected to BOOT_. Both SMPS1 and SMPS2 PWM controllers consist of a triple-mode feedback network and multiplexer, a multi-input PWM comparator, high-side and low-side gate drivers and logic. In addition, SMPS2 can also use REFIN2 to track its output from 0.5V to 2.5V. The ISL6237 contains faultprotection circuits that monitor the main PWM outputs for undervoltage and overvoltage conditions. A power-on sequence block controls the power-up timing of the main PWMs and monitors the outputs for undervoltage faults. The ISL6237 includes an adjustable low drop-out linear regulator. The bias generator blocks include the linear regulator, a 2V precision reference and automatic bootstrap switchover circuit. The synchronous-switch gate drivers are directly powered from PVCC, while the high-side switch gate drivers are indirectly powered from PVCC through an external capacitor and an internal Schottky diode boost circuit. An automatic bootstrap circuit turns off the LDO linear regulator and powers the device from BYP if LDOREFIN is set to GND or VCC. See Table 1.
TABLE 1. LDO OUTPUT VOLTAGE TABLE LDO VOLTAGE VOLTAGE at BYP VOLTAGE at BYP CONDITIONS LDOREFIN < 0.3V, BYP > 4.63V LDOREFIN > VCC - 1V, BYP > 3V COMMENT Internal LDO is disabled. Internal LDO is disabled.
FREE-RUNNING, CONSTANT ON-TIME PWM CONTROLLER WITH INPUT FEED-FORWARD The constant on-time PWM control architecture is a pseudo-fixed-frequency, constant on-time, current-mode type with voltage feed forward. The constant on-time PWM control architecture relies on the output ripple voltage to provide the PWM ramp signal; thus the output filter capacitor's ESR acts as a current-feedback resistor. The high-side switch on-time is determined by a one-shot whose period is inversely proportional to input voltage and directly proportional to output voltage. Another one-shot sets a minimum off-time (300ns typ). The on-time one-shot triggers when the following conditions are met: the error comparator's output is high, the synchronous rectifier current is below the current-limit threshold, and the minimum off time one-shot has timed out. The controller utilizes the valley point of the output ripple to regulate and determine the off time. On-Time One-Shot (tON) Each PWM core includes a one-shot that sets the high-side switch on-time for each controller. Each fast, low-jitter, adjustable one-shot includes circuitry that varies the on-time in response to battery and output voltage. The high-side switch on-time is inversely proportional to the battery voltage as measured by the VIN input and proportional to the output voltage. This algorithm results in a nearly constant switching frequency despite the lack of a fixed-frequency clock generator. The benefit of a constant switching frequency is that the frequency can be selected to avoid noise-sensitive frequency regions:
K ( V OUT + I LOAD r DSON ( LOWERQ ) ) t ON = ----------------------------------------------------------------------------------------------------V IN (EQ. 1)
See Table 2 for approximate K- factors. Switching frequency increases as a function of load current due to the increasing drop across the synchronous rectifier, which causes a faster inductor-current discharge ramp. On-times translate only roughly to switching frequencies. The on-times guaranteed in the Electrical Characteristics are influenced by switching delays in the external high-side power MOSFET. Also, the dead-time effect increases the effective on-time, reducing the switching frequency. It occurs only in PWM mode (SKIP# = VCC) and during dynamic output voltage transitions when the inductor current reverses at light or negative load currents. With reversed inductor current, the inductor's EMF causes PHASE to go high earlier than normal, extending the on-time by a period equal to the UGATE-rising dead time.
FN6418.1 March 16, 2007
19
ISL6237
.
TABLE 2. APPROXIMATE K-FACTOR ERRORS APPROXIMATE SWITCHING K-FACTOR FREQUENCY K-FACTOR ERROR (%) (kHz) (s) 400 500 200 300 2.5 2.0 5.0 3.3 10
For loads above the critical conduction point, the actual switching frequency is:
V OUT + V DROP1 f = -----------------------------------------------------t ON ( V IN + V DROP2 ) (EQ. 2)
SMPS (tON = GND, REF, or OPEN), VOUT1 (tON = GND), VOUT2 (tON = VCC), VOUT1 (tON = VCC, REF, or OPEN), VOUT2
where:
10 10 10
* VDROP1 is the sum of the parasitic voltage drops in the inductor discharge path, including synchronous rectifier, inductor, and PC board resistances * VDROP2 is the sum of the parasitic voltage drops in the charging path, including high-side switch, inductor, and PC board resistances * tON is the on-time calculated by the ISL6237
20
FN6418.1 March 16, 2007
ISL6237
VIN: 5.5V to 25V 5V C5 1F
C8 1F PVCC VIN C10 10F
Q3a SI4816BDY
VCC
LDO LDOREFIN BOOT2 UGATE2 PHASE2 LGATE2 PGND OUT2
NC GND C1 10 10F Q1 IRF7821
BOOT1 UGATE1 C9 0.1F PHASE1
Q3b
OUT1 - PCI-e L1: 3.3H 1.25V/5A
C4 0.22F
OUT2-GFX L2: 2.2H TRACK REFIN2/10A
C11 330F 9m 6.3V R1 7.87k
LGATE1 OUT1 VCC 5V FB1 TIED TO GND = 5V FB1 TIED TO VCC = 1.5V R3 200k EN1 BYP FB1 AGND ILIM1 SKIP# EN_LDO
Q2 IRF7832
C2 2 x 330F 4m 6.3V
ISL6237
EN2
VCC
REFIN2 ILIM2
R2 10k
R5 200k C7 0.1F
REFIN2: STATIC 0V TO 2.5V REFIN2 TIED TO 3.3V = 1.05V REFIN2 TIED TO VCC = 3.3V VCC VCC
REF
R4 200k
R6 200k
POK1 VCC TON PAD POK2
FREQUENCY-DEPENDENT COMPONENTS 1.25V/1.05V SMPS SWITCHING FREQUENCY L1 L2 C2 C11 tON = VCC 200kHz/300kHz 3.3H 2.7H 2 x 330F 330F
FIGURE 62. ISL6237 TYPICAL GFX APPLICATION CIRCUIT
21
FN6418.1 March 16, 2007
ISL6237
VIN: 5.5V to 25V 5V C5 1F C8 1F PVCC VIN C10 10F
Q3a SI4816BDY
VCC
LDOREFIN TIED TO GND = 5V LDOREFIN TIED TO VCC = 3.3V LDO LDO VCC C1 10 10F
Q1a
LDOREFIN BOOT2 UGATE2 PHASE2 LGATE2 PGND OUT2
C6 F 4.7F
BOOT1 UGATE1
OUT1 1.5V/5A
L1: 3.3H
C9 0.1F PHASE1
Q3b
C4 0.22F
OUT2 L2: 2.2F 1.05V/5A
C11 330F 9m 6.3V
LGATE1 OUT1 VCC 3.3V VCC EN1 BYP FB1 R3 200k AGND ILIM1 SKIP# ON EN_LDO OFF
Q1b SI4816BDY
C2 330F 4m 6.3V
ISL6237
EN2
VCC REFIN2: STATIC 0V TO 2.5V REFIN2 TIED TO 3.3V = 1.05V REFIN2 TIED TO VCC = 3.3V VCC C7 0.1F VCC
FB1 TIED TO GND = 5V FB1 TIED TO VCC = 1.5V
REFIN2 ILIM2
R5 200k
REF
R4 200k
R6 200k
POK1 VCC TON PAD POK2
FREQUENCY-DEPENDENT COMPONENTS 1.5V/1.05V SMPS SWITCHING FREQUENCY L1 L2 C2 C11 tON = VCC 200kHz/300kHz 3.3H 2.7H 330F 330F
FIGURE 63. ISL6237 TYPICAL SYSTEM REGULATOR APPLICATION CIRCUIT
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ISL6237
TON SKIP#
BOOT1 UGATE1
BOOT2 UGATE2
PHASE1 PVCC LGATE1 SMPS1 SYNCH. PWM BUCK CONTROLLER SMPS2 SYNCH. PWM BUCK CONTROLLER PVCC
PHASE2
LGATE2
GND
PGND ILIM2
ILIM1
EN1 POK1 OUT1 SW THRES. +
EN2 POK2 OUT2
FB1 OUT1 BYP
REFIN2 OUT2 POK2
POK1 LDO LDO LDOREFIN INTERNAL LOGIC 10 VIN PVCC VCC
EN_LDO POWER-ON EN1 EN2 SEQUENCE CLEAR FAULT LATCH THERMAL THERMAL SHUTDOWN SHUTDOWN REF REF
FIGURE 64. DETAIL FUNCTIONAL DIAGRAM ISL6237
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ISL6237
TON VIN + OUT_ MIN. tOFF Q TRIG ONE SHOT Q RQ SQ Q REFIN2 (SMPS2) VREF COMP SLOPE COMP + + + + + TO UGATE_DRIVER
5A + VCC
PHASE_ OUT_
0.9VREF + + +
FB_ 1.1VREF
0.7VREF
FIGURE 65. PWM CONTROLLER (ONE SIDE ONLY)
24
+
+ + +
FB DECODER
+ + +
+
+
ILIM_
BOOT UV DETECT
BOOT_
TO LGATE_ DRIVER S Q SQ RQ Q SKIP#
PGOOD_
OV_LATCH_ UV_LATCH_
FAULT FAULT LATCH LATCH LOGIC
20ms BLANKING
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ISL6237 Automatic Pulse-Skipping Switchover (Idle Mode)
In Idle Mode (SKIP# = GND), an inherent automatic switchover to PFM takes place at light loads. This switchover is affected by a comparator that truncates the low-side switch on-time at the inductor current's zero crossing. This mechanism causes the threshold between pulse-skipping PFM and non skipping PWM operation to coincide with the boundary between continuous and discontinuous inductor-current operation (also known as the critical conduction point):
K V OUT V IN - V OUT I LOAD ( SKIP ) = ----------------------- ------------------------------2L V IN (EQ. 3)
The switching waveforms may appear noisy and asynchronous when light loading causes pulse-skipping operation, but this is a normal operating condition that results in high light-load efficiency. Trade-offs in PFM noise vs light-load efficiency are made by varying the inductor value. Generally, low inductor values produce a broader efficiency vs load curve, while higher values result in higher full-load efficiency (assuming that the coil resistance remains fixed) and less output voltage ripple. Penalties for using higher inductor values include larger physical size and degraded load-transient response (especially at low input-voltage levels). DC output accuracy specifications refer to the trip level of the error comparator. When the inductor is in continuous conduction, the output voltage has a DC regulation higher than the trip level by 50% of the ripple. In discontinuous conduction (SKIP# = GND, light load), the output voltage has a DC regulation higher than the trip level by approximately 1.0% due to slope compensation.
where K is the on-time scale factor (see "On-Time One-Shot (tON)" on page 19). The load-current level at which PFM/PWM crossover occurs, ILOAD(SKIP), is equal to half the peak-to-peak ripple current, which is a function of the inductor value (Figure 66). For example, in the ISL6237 typical application circuit with VOUT1 = 5V, VIN = 12V, L = 7.6H, and K = 5s, switchover to pulse-skipping operation occurs at ILOAD = 0.96A or about on-fifth full load. The crossover point occurs at an even lower value if a swinging (soft-saturation) inductor is used.
I t INDUCTOR CURRENT = VIN -V OUT L IPEAK
Forced-PWM Mode
The low-noise, forced-PWM (SKIP# = VCC) mode disables the zero-crossing comparator, which controls the low-side switch on-time. Disabling the zero-crossing detector causes the low-side, gate-drive waveform to become the complement of the high-side, gate-drive waveform. The inductor current reverses at light loads as the PWM loop strives to maintain a duty ratio of VOUT/VIN. The benefit of forced-PWM mode is to keep the switching frequency fairly constant, but it comes at a cost: the no-load battery current can be 10mA to 50mA, depending on switching frequency and the external MOSFETs. Forced-PWM mode is most useful for reducing audio-frequency noise, improving load-transient response, providing sink-current capability for dynamic output voltage adjustment, and improving the cross-regulation of multiple-output applications that use a flyback transformer or coupled inductor.
ILOAD = IPEAK/2
0
ON-TIME
TIME
FIGURE 66. ULTRASONIC CURRENT WAVEFORMS
40s (MAX) INDUCTOR CURRENT
Enhanced Ultrasonic Mode (25kHz (min) Pulse Skipping)
Leaving SKIP# unconnected or connecting SKIP# to REF activates a unique pulse-skipping mode with a minimum switching frequency of 25kHz. This ultrasonic pulse-skipping mode eliminates audio-frequency modulation that would otherwise be present when a lightly loaded controller automatically skips pulses. In ultrasonic mode, the controller automatically transitions to fixed-frequency PWM operation when the load reaches the same critical conduction point (ILOAD(SKIP)). An ultrasonic pulse occurs when the controller detects that no switching has occurred within the last 20s. Once triggered, the ultrasonic controller pulls LGATE high, turning on the low-side MOSFET to induce a negative inductor
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Zero-Crossing ZERO-CROSSING DETECTION 0A FB < REG.POINT
ON-TIME (t ON )
FIGURE 67. ULTRASONIC CURRENT WAVEFORMS
25
ISL6237
current. After FB drops below the regulation point, the controller turns off the low-side MOSFET (LGATE pulled low) and triggers a constant on-time (UGATE driven high). When the on-time has expired, the controller re-enables the low-side MOSFET until the controller detects that the inductor current dropped below the zero-crossing threshold. Starting with a LGATE pulse greatly reduces the peak output voltage when compared to starting with a UGATE pulse, as long as VFB < VREF, LGATE is off and UGATE is on, similar to pure SKIP mode. temperature rise. The ISL6237 controller has a built-in 5A current source as shown in Figure 69. Place the hottest power MOSFETs as close to the IC as possible for best thermal coupling. The current limit varies with the onresistance of the synchronous rectifier. When combined with the undervoltage-protection circuit, this current-limit method is effective in almost every circumstance. A negative current limit prevents excessive reverse inductor currents when VOUT sinks current. The negative current-limit threshold is set to approximately 120% of the positive current limit and therefore tracks the positive current limit when ILIM_ is adjusted. The current-limit threshold is adjusted with an external resistor for ISL6237 at ILIM_. The current-limit threshold adjustment range is from 20mV to 200mV. In the adjustable mode, the current-limit threshold voltage is 1/10th the voltage at ILIM_. The voltage at ILIM pin is the product of 5A * RILIM. The threshold defaults to 100mV when ILIM_ is connected to VCC. The logic threshold for switch-over to the 100mV default value is approximately VCC - 1V. The PC board layout guidelines should be carefully observed to ensure that noise and DC errors do not corrupt the current-sense signals at PHASE_.
Reference and Linear Regulator (REF and LDO)
The 2V reference (REF) is accurate to 1% over temperature, making REF useful as a precision system reference. Bypass REF to GND with a 0.1F (min) capacitor. REF can supply up to 50A for external loads. An internal regulator produces a fixed 5V (LDOREFIN < 0.2V) or 3.3V (LDOREFIN > VCC - 1V). In an adjustable mode, the LDO output can be set from 0.7V to 4.5V. The LDO output voltage is equal to two times the LDOREFIN voltage. The LDO regulator can supply up to 100mA for external loads. Bypass LDO with a minimum 4.7F ceramic capacitor. When the LDOREFIN < 0.2V and BYP voltage is 5V, the LDO bootstrap-switchover to an internal 0.7 P-channel MOSFET switch connects BYP to LDO pin while simultaneously shutting down the internal linear regulator. These actions bootstrap the device, powering the loads from the BYP input voltages, rather than through internal linear regulators from the battery. Similarly, when the BYP = 3.3V and LDOREFIN = VCC, the LDO bootstrap-switchover to an internal 1.5 p-channel MOSFET switch connects BYP to LDO pin while simultaneously shutting down the internal linear regulator. No switchover action in adjustable mode.
I PEAK INDUCTOR CURRENT
I LOAD
I
I LIMIT I LOAD(MAX) I ILIM (VAL) = I LOAD - 2 TIME
Current-Limit Circuit (ILIM_) with rDS(ON) Temperature Compensation
The current-limit circuit employs a "valley" current-sensing algorithm. The ISL6237 uses the on-resistance of the synchronous rectifier as a current-sensing element. If the magnitude of the current-sense signal at PHASE_ is above the current-limit threshold, the PWM is not allowed to initiate a new cycle. The actual peak current is greater than the currentlimit threshold by an amount equal to the inductor ripple current. Therefore, the exact current-limit characteristic and maximum load capability are a function of the current-limit threshold, inductor value and input and output voltage. For lower power dissipation, the ISL6237 uses the on-resistance of the synchronous rectifier as the current-sense element. Use the worst-case maximum value for rDS(ON) from the MOSFET data sheet. Add some margin for the rise in rDS(ON) with temperature. A good general rule is to allow 0.5% additional resistance for each C of
FIGURE 68. "VALLEY" CURRENT LIMIT THRESHOLD POINT
ILIM_ + 5A 5 RILIM VILIM + + + + 9R VCC R TO CURRENT LIMIT LOGIC
FIGURE 69. CURRENT LIMIT BLOCK DIAGRAM
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ISL6237 MOSFET Gate Drivers (UGATE_, LGATE_)
The UGATE_ and LGATE_ gate drivers sink 2.0A and 3.3A respectively of gate drive, ensuring robust gate drive for high-current applications. The UGATE_ floating high-side MOSFET drivers are powered by diode-capacitor charge pumps at BOOT_. The LGATE_ synchronous-rectifier drivers are powered by PVCC. The internal pull-down transistors that drive LGATE_ low have a 0.6 typical on-resistance. These low on-resistance pull-down transistors prevent LGATE_ from being pulled up during the fast rise time of the inductor nodes due to capacitive coupling from the drain to the gate of the low-side synchronous-rectifier MOSFETs. However, for high-current applications, some combinations of high- and low-side MOSFETs may cause excessive gate-drain coupling, which leads to poor efficiency and EMI-producing shoot-through currents. Adding a 1 resistor in series with BOOT_ increases the turn-on time of the high-side MOSFETs at the expense of efficiency, without degrading the turn-off time (Figure 70). Adaptive dead-time circuits monitor the LGATE_ and UGATE_ drivers and prevent either FET from turning on until the other is fully off. This algorithm allows operation without shoot-through with a wide range of MOSFETs, minimizing delays and maintaining efficiency. There must be low-resistance, low-inductance paths from the gate drivers to the MOSFET gates for the adaptive dead-time circuit to work properly. Otherwise, the sense circuitry interprets the MOSFET gate as "off" when there is actually charge left on the gate. Use very short, wide traces measuring 10 to 20 squares (50 mils to 100 mils wide if the MOSFET is 1" from the device).
5V BOOT_ 10 10 VIN
maximum operating duty cycle (this occurs at minimum input voltage). The minimum gate to source voltage (VGS(MIN)) is determined by:
C BOOT V GS ( MIN ) = PVCC -------------------------------------C BOOT + C GS (EQ. 4)
where: * PVCC is 5V * CGS is the gate capacitance of the high-side MOSFET
Boost-Supply Refresh Monitor
In pure skip mode, the converter frequency can be very low with little to no output loading. This produces very long off times, where leakage can bleed down the BOOT capacitor voltage. If the voltage falls too low, the converter may not be able to turn on UGATE when the output voltage falls to the reference. To prevent this, the ISL6237 monitors the BOOT capacitor voltage, and if it falls below 3V, it initiates an LGATE pulse, which will refresh the BOOT voltage.
POR, UVLO, and Internal Digital Soft-Start
Power-on reset (POR) occurs when VIN rises above approximately 3V, resetting the undervoltage, overvoltage, and thermal-shutdown fault latches. PVCC undervoltage-lockout (UVLO) circuitry inhibits switching when PVCC is below 4V. LGATE_ is low during UVLO. The output voltages begin to ramp up once PVCC exceeds its 4V UVLO and REF is in regulation. The internal digital soft-start timer begins to ramp up the maximum-allowed current limit during start-up. The 1.7ms ramp occurs in five steps. The step size are 20%, 40%, 60%, 80% and 100% of the positive current limit value.
Power-Good Output (POK_)
The POK_ comparator continuously monitors both output voltages for undervoltage conditions. POK_ is actively held low in shutdown, standby, and soft-start. POK1 releases and digital soft-start terminates when VOUT1 outputs reach the error-comparator threshold. POK1 goes low if VOUT1 output turns off or is 10% below its nominal regulation point. POK1 is a true open-drain output. Likewise, POK2 is used to monitor VOUT2.
UGATE_ C BOOT
Q1
OUT_ PHASE_
ISL6237 ISL88734
Fault Protection
The ISL6237 provides overvoltage/undervoltage fault protection in the buck controllers. Once activated, the controller continuously monitors the output for undervoltage and overvoltage fault conditions. OVERVOLTAGE PROTECTION When the output voltage of VOUT1 is 11% (16% for VOUT2) above the set voltage, the overvoltage fault protection activates. This latches on the synchronous rectifier MOSFET with 100% duty cycle, rapidly discharging the output capacitor until the negative current limit is achieved. Once
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FIGURE 70. REDUCING THE SWITCHING-NODE RISE TIME
Boost-Supply Capacitor Selection (Buck)
The boost capacitor should be 0.1F to 4.7F, depending on the input and output voltages, external components, and PC board layout. The boost capacitance should be as large as possible to prevent it from charging to excessive voltage, but small enough to adequately charge during the minimum low-side MOSFET conduction time, which happens at
27
ISL6237
negative current limit is met, UGATE is turned on for a minimum on-time, followed by another LGATE pulse until negative current limit. This effectively regulates the discharge current at the negative current limit in an effort to prevent excessively large negative currents that cause potentially damaging negative voltages on the load. Once an overvoltage fault condition is set, it can only be reset by toggling SHDN#, EN_, or cycling VIN (POR). UNDERVOLTAGE PROTECTION When the output voltage drops below 70% of its regulation voltage for at least 100s, the controller sets the fault latch and begins the discharge mode (see the following Shutdown and Output Discharge sections). UVP is ignored for at least 20ms (typical), after start-up or after a rising edge on EN_. Toggle EN_ or cycle VIN (POR) to clear the undervoltage fault latch and restart the controller. UVP only applies to the buck outputs. THERMAL PROTECTION The ISL6237 has thermal shutdown to protect the devices from overheating. Thermal shutdown occurs when the die temperature exceeds +150C. All internal circuitry shuts down during thermal shutdown. The ISL6237 may trigger thermal shutdown if LDO_ is not bootstrapped from OUT_ while applying a high input voltage on VIN and drawing the maximum current (including short circuit) from LDO_. Even if LDO_ is bootstrapped from OUT_, overloading the LDO_ causes large power dissipation on the bootstrap switches, which may result in thermal shutdown. Cycling EN_, EN_LDO, or VIN (POR) ends the thermal-shutdown state.
Discharge Mode (Soft-Stop)
When a transition to standby or shutdown mode occurs, or the output undervoltage fault latch is set, the outputs discharge to GND through an internal 25 switch. The reference remains active to provide an accurate threshold and to provide overvoltage protection.
Shutdown Mode
The ISL6237 SMPS1, SMPS2 and LDO have independent enabling control. Drive EN1, EN2 and EN_LDO below the precise input falling-edge trip level to place the ISL6237 in its low-power shutdown state. The ISL6237 consumes only 20A of quiescent current while in shutdown. Both SMPS outputs are discharged to 0V through a 25 switch.
Power-Up Sequencing and On/Off Controls (EN_)
EN1 and EN2 control SMPS power-up sequencing. EN1 or EN2 rising above 2.4V enables the respective outputs. EN1 or EN2 falling below 1.6V disables the respective outputs. Connecting EN1 or EN2 to REF will force its outputs off while the other output is below regulation. The sequenced SMPS will start once the other SMPS reaches regulation. The second SMPS remains on until the first SMPS turns off, the device shuts down, a fault occurs or PVCC goes into undervoltage lockout. Both supplies begin their power-down sequence immediately when the first supply turns off. Driving EN_ below 0.8V clears the overvoltage, undervoltage and thermal fault latches.
TABLE 3. OPERATING-MODE TRUTH TABLE MODE Power-Up Run Overvoltage Protection Undervoltage Protection Discharge CONDITION PVCC < UVLO threshold. EN_LDO = high, EN1 or EN2 enabled. Either output > 111% (VOUT1) or 116% (VOUT2) of nominal level. Either output < 70% of nominal after 20ms time-out expires and output is enabled. Either SMPS output is still high in either standby mode or shutdown mode EN1, EN2 < startup threshold, EN_LDO = High EN1, EN2, EN_LDO = low TJ > +150C COMMENT Transitions to discharge mode after a VIN POR and after REF becomes valid. LDO and REF remain active. Normal operation LGATE_ is forced high. LDO and REF are active. Exited by a VIN POR, or by toggling EN1 or EN2. The internal 25 switch turns on. LDO and REF are active. Exited by a VIN POR or by toggling EN1 or EN2. Discharge switch (25) connects OUT_ to GND. One output may still run while the other is in discharge mode. Activates when PVCC is in UVLO, or transition to UVLO, standby, or shutdown has begun. LDO and REF active. LDO and REF are active. Discharge switch (25) connects OUT_ to PGND. All circuitry off. All circuitry off. Exited by VIN POR or cycling EN_.
Standby Shutdown Thermal Shutdown
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TABLE 4. SHUTDOWN AND STANDBY CONTROL LOGIS VEN_LDO LOW ">2.5" HIGH ">2.5" HIGH ">2.5" HIGH ">2.5" HIGH ">2.5" HIGH ">2.5" HIGH VEN1 (V) LOW LOW HIGH HIGH LOW HIGH REF VEN2 (V) LOW LOW HIGH LOW HIGH REF HIGH LDO OFF ON ON ON ON ON ON SMPS1 OFF OFF ON ON OFF ON ON (AFTER SMPS2 IS UP) SMPS2 OFF OFF ON OFF ON ON (AFTER SMPS1 IS UP) ON
Adjustable-Output Feedback (Dual-Mode FB)
Connect FB1 to GND to enable the fixed 5V or tie FB1 to VCC to set the fixed 1.5V output. Connect a resistive voltage-divider at FB1 between OUT1 and GND to adjust the respective output voltage between 0.7V and 5.5V (Figure 71). Choose R2 to be approximately 10k and solve for R1 using Equation 5.
V OUT1 R 1 = R 2 ------------------ - 1 V FB1
3. Switching Frequency. This choice determines the basic trade-off between size and efficiency. The optimal frequency is largely a function of maximum input voltage and MOSFET switching losses. 4. Inductor Ripple Current Ratio (LIR). LIR is the ratio of the peak-peak ripple current to the average inductor current. Size and efficiency trade-offs must be considered when setting the inductor ripple current ratio. Low inductor values cause large ripple currents, resulting in the smallest size, but poor efficiency and high output noise. Also, total output ripple above 3.5% of the output regulation will cause controller to trigger out-of-bound condition. The minimum practical inductor value is one that causes the circuit to operate at critical conduction (where the inductor current just touches zero with every cycle at maximum load). Inductor values lower than this grant no further size-reduction benefit. The ISL6237 pulse-skipping algorithm (SKIP# = GND) initiates skip mode at the critical conduction point, so the inductor's operating point also determines the load current at which PWM/PFM switchover occurs. The optimum LIR point is usually found between 25% and 50% ripple current.
VIN
(EQ. 5)
where VFB1 = 0.7V nominal. Likewise, connect REFIN2 to VCC to enable the fixed 3.3V or tie REFIN2 to a 3.3V supply to set the fixed 1.05V output. Set REFIN2 from 0 to 2.50V for SMPS2 tracking mode (Figure 72)
VR R3 = R4 ------------------ - 1 V
OUT2
(EQ. 6)
where: * VR = 2V nominal (if tied to REF)
Design Procedure
Establish the input voltage range and maximum load current before choosing an inductor and its associated ripple-current ratio (LIR). The following four factors dictate the rest of the design: 1. Input Voltage Range. The maximum value (VIN(MAX)) must accommodate the maximum AC adapter voltage. The minimum value (VIN(MIN)) must account for the lowest input voltage after drops due to connectors, fuses and battery selector switches. Lower input voltages result in better efficiency. 2. Maximum Load Current. The peak load current (ILOAD(MAX)) determines the instantaneous component stress and filtering requirements and thus drives output capacitor selection, inductor saturation rating and the design of the current-limit circuit. The continuous load current (ILOAD) determines the thermal stress and drives the selection of input capacitors, MOSFETs and other critical heat-contributing components.
UGATE1 UGATE_ UGATE1 ISL88732 ISL6237 ISL88733 ISL88734 ISL6237 LGATE_ LGATE1 LGATE1
Q3 OUT1
Q4
OUT1 VOUT_ OUT1 FB1 FB1 FB_
R1
R2
FIGURE 71. SETTING VOUT1 WITH A RESISTOR DIVIDER
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ISL6237
.
VIN
Determining the Current Limit
The minimum current-limit threshold must be great enough to support the maximum load current when the current limit is at the minimum tolerance value. The valley of the inductor current occurs at ILOAD(MAX) minus half of the ripple current; therefore:
I LIMIT ( LOW ) > I LOAD ( MAX ) - [ ( LIR 2 ) I LOAD ( MAX ) ] (EQ. 11)
UGATE2 UGATE_ UGATE2 ISL88732 ISL88733 ISL6237 ISL88734 LGATE_ LGATE2 LGATE2
Q1
OUT2
Q2 Q2
where: ILIMIT(LOW) = minimum current-limit threshold voltage divided by the rDS(ON) of Q2/Q4. Use the worst-case maximum value for rDS(ON) from the MOSFET Q2/Q4 data sheet and add some margin for the rise in rDS(ON) with temperature. A good general rule is to allow 0.2% additional resistance for each C of temperature rise. Examining the 5A circuit example with a maximum rDS(ON) = 5m at room temperature. At +125C reveals the following:
I LIMIT ( LOW ) = ( 25mV ) ( ( 5m x 1.2 ) > 5A - ( 0.35 2 )5A ) (EQ. 12) 4.17A > 4.12A (EQ. 13)
VOUT_ OUT2 OUT2 FB_ REFIN2 REFIN2 R4 R3 VR
FIGURE 72. SETTING VOUT2 WITH A VOLTAGE DIVIDER FOR TRACKING
Inductor Selection
The switching frequency (on-time) and operating point (% ripple or LIR) determine the inductor value as follows:
V OUT _ ( V IN + V OUT _ ) L = -------------------------------------------------------------------V IN f LIR I LOAD ( MAX ) (EQ. 7)
4.17A is greater than the valley current of 4.12A, so the circuit can easily deliver the full-rated 5A using the 30mV nominal current-limit threshold voltage.
Example: ILOAD(MAX) = 5A, VIN = 12V, VOUT2 = 5V, f = 200kHz, 35% ripple current or LIR = 0.35:
5V ( 12V - 5V ) L = ----------------------------------------------------------------- = 8.3H 12V 200kHz 0.35 5A (EQ. 8)
Output Capacitor Selection
The output filter capacitor must have low enough equivalent series resistance (ESR) to meet output ripple and load-transient requirements, yet have high enough ESR to satisfy stability requirements. The output capacitance must also be high enough to absorb the inductor energy while transitioning from full-load to no-load conditions without tripping the overvoltage fault latch. In applications where the output is subject to large load transients, the output capacitor's size depends on how much ESR is needed to prevent the output from dipping too low under a load transient. Ignoring the sag due to finite capacitance:
V DIP R SER --------------------------------I LOAD ( MAX ) (EQ. 14)
Find a low-loss inductor having the lowest possible DC resistance that fits in the allotted dimensions. Ferrite cores are often the best choice. The core must be large enough not to saturate at the peak inductor current (IPEAK):
IPEAK = I LOAD ( MAX ) + [ ( LIR 2 ) I LOAD ( MAX ) ] (EQ. 9)
The inductor ripple current also impacts transient response performance, especially at low VIN - VOUT_ differences. Low inductor values allow the inductor current to slew faster, replenishing charge removed from the output filter capacitors by a sudden load step. The peak amplitude of the output transient (VSAG) is also a function of the maximum duty factor, which can be calculated from the on-time and minimum off-time:
V OUT _ 2 ( I LOAD ( MAX ) ) L K ------------------ + t OFF ( MIN ) V IN V SAG = --------------------------------------------------------------------------------------------------------------------------V IN - V OUT 2 C OUT V OUT K ------------------------------- - t V IN OFF ( MIN ) (EQ. 10)
where VDIP is the maximum-tolerable transient voltage drop. In non-CPU applications, the output capacitor's size depends on how much ESR is needed to maintain an acceptable level of output voltage ripple:
VP - P R ESR ----------------------------------------------L IR I LOAD ( MAX ) (EQ. 15)
where minimum off-time = 0.35s (max) and K is from Table 2.
where VP-P is the peak-to-peak output voltage ripple. The actual capacitance value required relates to the physical size needed to achieve low ESR, as well as to the chemistry of the capacitor technology. Thus, the capacitor is usually selected by ESR and voltage rating rather than by
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capacitance value (this is true of tantalum, OS-CON, and other electrolytic-type capacitors). When using low-capacity filter capacitors such as polymer types, capacitor size is usually determined by the capacity required to prevent VSAG and VSOAR from tripping the undervoltage and overvoltage fault latches during load transients in ultrasonic mode. For low input-to-output voltage differentials (VIN/ VOUT < 2), additional output capacitance is required to maintain stability and good efficiency in ultrasonic mode. The amount of overshoot due to stored inductor energy can be calculated as:
I PEAK L V SOAR = ----------------------------------------------2 C OUT V OUT_
2
Ensure that conduction losses plus switching losses at the maximum input voltage do not exceed the package ratings or violate the overall thermal budget. Choose a synchronous rectifier (Q2/Q4) with the lowest possible rDS(ON). Ensure the gate is not pulled up by the high-side switch turning on due to parasitic drain-to-gate capacitance, causing cross-conduction problems. Switching losses are not an issue for the synchronous rectifier in the buck topology since it is a zero-voltage switched device when using the buck topology.
MOSFET Power Dissipation
Worst-case conduction losses occur at the duty-factor extremes. For the high-side MOSFET, the worst-case power dissipation (PD) due to the MOSFET's rDS(ON) occurs at the minimum battery voltage:
V OUT _ 2 PD ( Q H Resistance ) = ------------------------ ( I LOAD ) r DS( ON ) V IN ( MIN ) (EQ. 18)
(EQ. 16)
where IPEAK is the peak inductor current.
Input Capacitor Selection
The input capacitors must meet the input-ripple-current (IRMS) requirement imposed by the switching current. The ISL6237 dual switching regulator operates at different frequencies. This interleaves the current pulses drawn by the two switches and reduces the overlap time where they add together. The input RMS current is much smaller in comparison than with both SMPSs operating in phase. The input RMS current varies with load and the input voltage. The maximum input capacitor RMS current for a single SMPS is given by:
V OUT ( V IN - V OUT _ ) I RMS I LOAD ------------------------------------------------------------ V IN (EQ. 17)
Generally, a small high-side MOSFET reduces switching losses at high input voltage. However, the rDS(ON) required to stay within package power-dissipation limits often limits how small the MOSFET can be. The optimum situation occurs when the switching (AC) losses equal the conduction (rDS(ON)) losses. Switching losses in the high-side MOSFET can become an insidious heat problem when maximum battery voltage is applied, due to the squared term in the CV2f switching-loss equation. Reconsider the high-side MOSFET chosen for adequate rDS(ON) at low battery voltages if it becomes extraordinarily hot when subjected to VIN(MAX). Calculating the power dissipation in NH (Q1/Q3) due to switching losses is difficult since it must allow for quantifying factors that influence the turn-on and turn-off times. These factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and PC board layout characteristics. The following switching-loss calculation provides only a very rough estimate and is no substitute for bench evaluation, preferably including verification using a thermocouple mounted on NH (Q1/Q3):
2 C RSS f SW I LOAD PD ( Q H Switching ) = ( V IN ( MAX ) ) ---------------------------------------------------- I GATE (EQ. 19)
When V IN = 2 V OUT _ ( D = 50% ) , IRMS has maximum current of I LOAD 2 . The ESR of the input-capacitor is important for determining capacitor power dissipation. All the power (IRMS2 x ESR) heats up the capacitor and reduces efficiency. Nontantalum chemistries (ceramic or OS-CON) are preferred due to their low ESR and resilience to power-up surge currents. Choose input capacitors that exhibit less than +10C temperature rise at the RMS input current for optimal circuit longevity. Place the drains of the high-side switches close to each other to share common input bypass capacitors.
Power MOSFET Selection
Most of the following MOSFET guidelines focus on the challenge of obtaining high load-current capability (>5A) when using high-voltage (>20V) AC adapters. Low-current applications usually require less attention. Choose a high-side MOSFET (Q1/Q3) that has conduction losses equal to the switching losses at the typical battery voltage for maximum efficiency. Ensure that the conduction losses at the minimum input voltage do not exceed the package thermal limits or violate the overall thermal budget.
where CRSS is the reverse transfer capacitance of QH (Q1/Q3) and IGATE is the peak gate-drive source/sink current. For the synchronous rectifier, the worst-case power dissipation always occurs at maximum battery voltage:
V OUT 2 PD ( Q L ) = 1 - ------------------------- I LOAD r DS ( ON ) V IN ( MAX ) (EQ. 20)
The absolute worst case for MOSFET power dissipation occurs under heavy overloads that are greater than
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ILOAD(MAX) but are not quite high enough to exceed the current limit and cause the fault latch to trip. To protect against this possibility, "overdesign" the circuit to tolerate:
I LOAD = I LIMIT ( HIGH ) + ( ( LIR ) 2 ) I LOAD ( MAX ) (EQ. 21)
dropout point, the inductor current is less able to increase during each switching cycle and VSAG greatly increases unless additional output capacitance is used. A reasonable minimum value for h is 1.5, but this can be adjusted up or down to allow trade-offs between VSAG, output capacitance and minimum operating voltage. For a given value of h, the minimum operating voltage can be calculated as:
( V OUT _ + V DROP ) V IN ( MIN ) = -------------------------------------------------- + V DROP2 - V DROP1 t OFF ( MIN ) h ----------------------------------- 1- K (EQ. 22)
where ILIMIT(HIGH) is the maximum valley current allowed by the current-limit circuit, including threshold tolerance and resistance variation.
Rectifier Selection
Current circulates from ground to the junction of both MOSFETs and the inductor when the high-side switch is off. As a consequence, the polarity of the switching node is negative with respect to ground. This voltage is approximately -0.7V (a diode drop) at both transition edges while both switches are off (dead time). The drop is I L r DS ( ON ) when the low-side switch conducts. The rectifier is a clamp across the synchronous rectifier that catches the negative inductor swing during the dead time between turning the high-side MOSFET off and the synchronous rectifier on. The MOSFETs incorporate a high-speed silicon body diode as an adequate clamp diode if efficiency is not of primary importance. Place a Schottky diode in parallel with the body diode to reduce the forward voltage drop and prevent the Q2/Q4 MOSFET body diodes from turning on during the dead time. Typically, the external diode improves the efficiency by 1% to 2%. Use a Schottky diode with a DC current rating equal to one-third of the load current. For example, use an MBR0530 (500mA-rated) type for loads up to 1.5A, a 1N5817 type for loads up to 3A, or a 1N5821 type for loads up to 10A. The rectifier's rated reverse breakdown voltage must be at least equal to the maximum input voltage, preferably with a 20% derating factor.
where VDROP1 and VDROP2 are the parasitic voltage drops in the discharge and charge paths (see "On-Time One-Shot (tON)" on page 19), tOFF(MIN) is from Electrical Specifications on page 3 and K is taken from Table 2. The absolute minimum input voltage is calculated with h = 1. Operating frequency must be reduced or h must be increased and output capacitance added to obtain an acceptable VSAG if calculated VIN(MIN) is greater than the required minimum input voltage. Calculate VSAG to be sure of adequate transient response if operation near dropout is anticipated. Dropout Design Example: ISL6237: With VOUT2 = 5V, fsw = 400kHz, K = 2.25s, tOFF(MIN) = 350ns, VDROP1 = VDROP2 = 100mV, and h = 1.5, the minimum VIN is:
( 5V + 0.1V ) V IN ( MIN ) = ---------------------------------------------- + 0.1V - 0.1V = 6.65V 0.35s 1.5 1 - ------------------------------- 2.25s (EQ. 23)
Calculating with h = 1 yields:
( 5V + 0.1V ) V IN ( MIN ) = ----------------------------------------- + 0.1V - 0.1V = 6.04V 0.35s 1 1 - -------------------------- 2.25s (EQ. 24)
Applications Information
Dropout Performance
The output voltage-adjust range for continuous-conduction operation is restricted by the nonadjustable 350ns (max) minimum off-time one-shot. Use the slower 5V SMPS for the higher of the two output voltages for best dropout performance in adjustable feedback mode. The duty-factor limit must be calculated using worst-case values for on- and off-times, when working with low input voltages. Manufacturing tolerances and internal propagation delays introduce an error to the TON K-factor. Also, keep in mind that transient-response performance of buck regulators operated close to dropout is poor, and bulk output capacitance must often be added (see Equation 10 on page 30). The absolute point of dropout occurs when the inductor current ramps down during the minimum off-time (IDOWN) as much as it ramps up during the on-time (IUP). The ratio h = IUP/IDOWN indicates the ability to slew the inductor current higher in response to increased load, and must always be greater than 1. As h approaches 1, the absolute minimum 32
Therefore, VIN must be greater than 6.65V. A practical input voltage with reasonable output capacitance would be 7.5V.
PC Board Layout Guidelines
Careful PC board layout is critical to achieve minimal switching losses and clean, stable operation. This is especially true when multiple converters are on the same PC board where one circuit can affect the other. Refer to the ISL6237 Evaluation Kit data sheet for a specific layout example. Mount all of the power components on the top side of the board with their ground terminals flush against one another, if possible. Follow these guidelines for good PC board layout: * Isolate the power components on the top side from the sensitive analog components on the bottom side with a ground shield. Use a separate PGND plane under the OUT1 and OUT2 sides (called PGND1 and PGND2). Avoid the introduction of AC currents into the PGND1 and PGND2
FN6418.1 March 16, 2007
ISL6237
ground planes. Run the power plane ground currents on the top side only, if possible. * Use a star ground connection on the power plane to minimize the crosstalk between OUT1 and OUT2. * Keep the high-current paths short, especially at the ground terminals. This practice is essential for stable, jitter-free operation. * Keep the power traces and load connections short. This practice is essential for high efficiency. Using thick copper PC boards (2oz vs 1oz) can enhance full-load efficiency by 1% or more. Correctly routing PC board traces must be approached in terms of fractions of centimeters, where a single m of excess trace resistance causes a measurable efficiency penalty. * PHASE_ (ISL6237) and GND connections to the synchronous rectifiers for current limiting must be made using Kelvin-sense connections to guarantee the current-limit accuracy with 8-pin SO MOSFETs. This is best done by routing power to the MOSFETs from outside using the top copper layer, while connecting PHASE_ traces inside (underneath) the MOSFETs. * When trade-offs in trace lengths must be made, it is preferable to allow the inductor charging path to be made longer than the discharge path. For example, it is better to allow some extra distance between the input capacitors and the high-side MOSFET than to allow distance between the inductor and the synchronous rectifier or between the inductor and the output filter capacitor. * Ensure that the OUT_ connection to COUT_ is short and direct. However, in some cases it may be desirable to deliberately introduce some trace length between the OUT_ connector node and the output filter capacitor. * Route high-speed switching nodes (BOOT_, UGATE_, PHASE_, and LGATE_) away from sensitive analog areas (REF, ILIM_, and FB_). Use PGND1 and PGND2 as an EMI shield to keep radiated switching noise away from the IC's feedback divider and analog bypass capacitors. * Make all pin-strap control input connections (SKIP#, ILIM_, etc.) to GND or VCC of the device. Mount the controller IC adjacent to the synchronous rectifier MOSFETs close to the hottest spot, preferably on the back side in order to keep UGATE_, GND, and the LGATE_ gate drive lines short and wide. The LGATE_ gate trace must be short and wide, measuring 50 mils to 100 mils wide if the MOSFET is 1" from the controller device. Group the gate-drive components (BOOT_ capacitor, VIN bypass capacitor) together near the controller device. Make the DC/DC controller ground connections as follows: 1. Near the device, create a small analog ground plane. 2. Connect the small analog ground plane to GND and use the plane for the ground connection for the REF and VCC bypass capacitors, FB dividers and ILIM resistors (if any). 3. Create another small ground island for PGND and use the plane for the VIN bypass capacitor, placed very close to the device. 4. Connect the GND and PGND planes together at the metal tab under device. On the board's top side (power planes), make a star ground to minimize crosstalk between the two sides. The top-side star ground is a star connection of the input capacitors and synchronous rectifiers. Keep the resistance low between the star ground and the source of the synchronous rectifiers for accurate current limit. Connect the top-side star ground (used for MOSFET, input, and output capacitors) to the small island with a single short, wide connection (preferably just a via). Create PGND islands on the layer just below the top-side layer (refer to the ISL6237 EV kit for an example) to act as an EMI shield if multiple layers are available (highly recommended). Connect each of these individually to the star ground via, which connects the top side to the PGND plane. Add one more solid ground plane under the device to act as an additional shield, and also connect the solid ground plane to the star ground via. Connect the output power planes (VCORE and system ground planes) directly to the output filter capacitor positive and negative terminals with multiple vias.
Layout Procedure
Place the power components first with ground terminals adjacent (Q2/Q4 source, CIN_, COUT_). If possible, make all these connections on the top layer with wide, copper-filled areas.
33
FN6418.1 March 16, 2007
ISL6237 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP)
L32.5x5B
32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VHHD-2 ISSUE C MILLIMETERS SYMBOL A A1 A2 A3 b D D1 D2 E E1 E2 e k L L1 N Nd Ne P 0.25 0.30 3.15 3.15 0.18 MIN 0.80 NOMINAL 0.90 0.20 REF 0.23 5.00 BSC 4.75 BSC 3.30 5.00 BSC 4.75 BSC 3.30 0.50 BSC 0.40 32 8 8 0.60 12 0.50 0.15 3.45 3.45 0.30 MAX 1.00 0.05 1.00 NOTES 9 9 5,8 9 7,8 9 7,8 8 10 2 3 3 9 9 Rev. 1 10/02 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Features and dimensions A2, A3, D1, E1, P & are present when Anvil singulation method is used and not present for saw singulation. 10. Depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (L1) maybe present. L minus L1 to be equal to or greater than 0.3mm.
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FN6418.1 March 16, 2007

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